As change of analog channels always happens after a transformation, for switching of channels of the converter it is possible to use the mode of continuous transformation. Usually for a of channels interruption on completion of transformation is used. the user has to take the following factors into account:
The flag of ADIF is dumped hardware when performing the corresponding. Other way to dump a flag - to write down in it "1". It is necessary to warn that at reading-modification-record ADCSR there can be a postponed interruption. Same concerns also the SBI and CB teams
Beat 6 - ADCBG - a choice of basic tension of ATsP - at installation of this bit on an entrance of ATsP moves the fixed tension 22+-05B when the bit is dumped, the entrance of ATsP is connected to one of external entrances according to installation of bits of MUX.MUX
By delivery a flash memory and memory of data are erased (contain FFh) and are ready to programming. Chips support high-voltage (12 parallel mode of programming and the low-voltage mode of programming. Tension + 12B is used only for permission of programming, this conclusion almost does not consume current. The mode of programming is provided for loading of a and data in system of the user (intrasystem. In both modes of programming memory of programs and data byte behind byte. For programming of EEPROM the cycle of automatic deleting when programming is provided in a consecutive.
SPI is activated as conducted at transfer of this conclusion to a low. During the work of SPI as leader, the direction of data transmission through this conclusion copes beaten DDB When the conclusion is transferred to a condition of input, connection of the tightening resistor copes beaten PORTB For more details see the description of SP port
Bit 7 - ADEN - Permission of ATsP. - At record logical "1" in this bit work of ATsP is allowed. At installation of bit in "0" ATsP it is switched off. At switching off of ATsP before the end of transformation, transformation does not.
PINC is not the register, to this address access to physical values of each of conclusions of port C is provided. When reading PORTC, data from the register latch are read, when reading PINC values attendees at conclusions of port are read.
PINB is not the register, to this address access to physical values of each of conclusions of port B is provided. When reading PORTB, data from the register latch are read, when reading PINB values attendees at conclusions of port are read.
PIND is not the register, to this address access to physical values of each of conclusions of port D is provided. When reading PORTD, data from the register latch are read, when reading PIND values attendees at conclusions of port are read.
The analog part of the processor and all analog components of an have to have the earth which is separately divorced on the printed-circuit board. The analog earth has to connect from a digital payment only in one point.
For service of port three registers are taken away: the register of data of PORTB (18h, 38h), the register of the direction of data - DDRB (17h, 37h) and legs of port B - PINB (16h, 36h). The address of legs of port B is intended only for reading, while the register of data and the register of the direction of data - for reading/record.